Suppose that a failure occurs in a computer system that uses, as a main memory, a byte-addressable nonvolatile memory, such as an MRAM, a PCM, or memristors, that can be directly connected to a memory bus of a processor. In that case, in order to be capable of continuing processing from a consistent state immediately before the failure occurred, the computer system needs to ensure ordering (property of orderliness) and atomicity (property of not stopping writing halfway) of writing into the nonvolatile memory performed by a computer program executed on the processor.
For example, a technique for ensuring the atomicity is known in which a capacitor is provided to ensure that a memory controller connected to a CPU (memory controller of a host device, from another point of view) completes the writing of data into the nonvolatile memory when power supply is lost.
With increases in operation speed of memories, recent years have seen the development of memory devices (such as Hybrid Memory Cube (HMC) and QuickPath Interconnect (QPI) memory devices) each provided thereon with a controller for writing of data into the memory. The memory controller of the processor (memory controller of the host device) connected to each of such memory devices recognizes that the writing of data is completed when transmission of the data (transmission of the writing target data) to the memory device is completed.
The writing target data that has been transmitted to the memory device is, however, written into the memory further via the controller of the memory device, so that the writing target data has not necessarily reached memory cells in the memory at the time when the memory controller of the processor recognizes that the writing of the data is completed. If power supply abnormality occurs (abnormality in power supplied from the power supply occurs) at this moment, a problem occurs in that the data currently being written is lost, or a problem occurs in that incomplete data is written, so that the atomicity cannot be ensured.